----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:00:00 04/07/2010 
-- Design Name: 
-- Module Name:    adr_decoder - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity adr_decoder is
    Port ( wb_adr_i : in  STD_LOGIC_VECTOR (24 downto 0);
           ram_ena_o : out  STD_LOGIC;
			  ram_adr_o : out STD_LOGIC_VECTOR (11 downto 0);
			  spi_ena_o : out STD_LOGIC;
			  spi_adr_o : out STD_LOGIC_VECTOR (1 downto 0);
			  gpio_ena_o : out STD_LOGIC;
			  gpio_adr_o : out STD_LOGIC_VECTOR (1 downto 0));
end adr_decoder;

architecture Behavioral of adr_decoder is

begin
P1: process(wb_adr_i)
begin
if wb_adr_i  >= "000000000000000000000000" and wb_adr_i  <= "000000000100000000000000" then -- 0x00 - 0x4000
ram_ena_o <= '1';
else 
ram_ena_o <= '0';
end if;

if wb_adr_i  >= "000000000100000000000100" and wb_adr_i  <= "000000000100000000010000" then --0x4004 - 0x410
spi_ena_o <= '1';
else 
spi_ena_o <= '0';
end if;

if wb_adr_i  >= "000000000100000000100000" and wb_adr_i  <= "000000000100000000101100" then --0x4020 - 0x402C
gpio_ena_o <= '1';
else 
gpio_ena_o <= '0';
end if;

ram_adr_o <= wb_adr_i(13 downto 2);
spi_adr_o <= wb_adr_i(3 downto 2);
gpio_adr_o <= wb_adr_i(3 downto 2);
end process;


end Behavioral;

